Tiliqua documentation

Warning

This manual is under construction and very incomplete!

Hardware

• Connections
  • Connections: Front
  • Connections: Back
  • Power: connecting +/- 12V
  • USB: the dbg and usb2 ports
  • Audio jacks: for touch, disconnect on boot
  • Display/DVI: disconnect when system off
• Electrical Design
  • Block Diagram (Tiliqua R4)
  • Pinouts and schematics
  • Tiliqua Motherboard
  • FPGA SoM (soldiercrab)
  • Audio Interface (eurorack-pmod R3.3)
• Changelist
  • Tiliqua R4
  • Tiliqua R3
  • Tiliqua R2
  • Tiliqua R1

Building & Flashing

• Prerequisites
• Getting Started
  • Building and flashing examples
    • Building
    • Flashing
  • Simulating designs
    • Simulating DSP cores
    • Simulating SoC cores
    • Simulating vectorscope core
  • Using the ILA
• Calibration
  • Background
  • Calibrating the ADCs/DACs
• Bootloader
  • User Interface
  • Bitstream Archives and Flash Memory Layout
  • Flashing the RP2040 and bootloader bitstream
    • Flashing Steps
  • Technical Details
    • Bootloader bitstream: ECP5
    • apfbug debugger firmware: RP2040
    • Recording new JTAG streams for RP2040
• Example Projects
  • SoC Projects
    • Background: Tiliqua SoC designs
    • All Projects
  • non-SoC projects
    • All Projects

Reference

• DSP Library
  • Philosophy
  • DSP Components
    • Delay Lines
    • Filters
    • Oscillators
    • Effects
    • VCAs
    • Mixing
    • Resampling
    • One-shot
    • Stream utilities
    • Miscellaneous utilities

Links

• Tiliqua on Crowd Supply
• Tiliqua on GitHub
• Homepage (apf.audio)